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Update README.md

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@@ -67,14 +67,10 @@ Our evaluation encompasses Verilog benchmarks, including VerilogEval and RTLLM.
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  | **CodeV-R1-distill (ours)** | 7B | Verilog RTL | 56.2% |
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  | **CodeV-R1 (ours)** | 7B | Verilog RTL | **72.9%** |
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- We also plot the results for RTLLM v1.1, including pass rate against model size and test-time scaling under different token/FLOPs budgets.
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  <div style="display: flex; gap: 10px;">
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  <img src="./assets/rtllm_acc_vs_model_size.png" alt="RTLLM TTS Results" width="1200">
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  </div>
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- <div style="display: flex; gap: 10px;">
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- <img src="./assets/rtllm_tts.png" alt="RTLLM TTS Results" width="500">
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- <img src="./assets/rtllm_tts_flops.png" alt="RTLLM TTS FLOPs Results" width="500">
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- </div>
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  ### 4. Usage
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  | **CodeV-R1-distill (ours)** | 7B | Verilog RTL | 56.2% |
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  | **CodeV-R1 (ours)** | 7B | Verilog RTL | **72.9%** |
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+ For RTLLM v1.1, we also plot results showing pass rate against model size.
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  <div style="display: flex; gap: 10px;">
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  <img src="./assets/rtllm_acc_vs_model_size.png" alt="RTLLM TTS Results" width="1200">
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  </div>
 
 
 
 
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  ### 4. Usage
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